PROTECTED ELECTRONIC CHIP

专利摘要:
An electronic chip, comprising: a doped semiconductor substrate (46) of a first conductivity type; a buried layer (36) doped with a second type of conductivity covering the substrate; a first box (37) doped with the first type of conductivity covering the buried layer; circuits (10, 24, 32) separated from the buried layer formed in and on the first well and / or in and on second wells (12, 26, 16) formed in the first well; and a polarization current detector (I) of the buried layer.
公开号:FR3057087A1
申请号:FR1659451
申请日:2016-09-30
公开日:2018-04-06
发明作者:Clement Champeix；Nicolas Borrel；Alexandre Sarafianos
申请人:STMicroelectronics Rousset SAS；
IPC主号:

专利说明:

Field
The present application relates to electronic chips, in particular electronic chips secured against attacks.
Presentation of the prior art
Electronic chips such as bank card chips contain confidential data that may be coveted by hackers. To obtain this information, a hacker can carry out an attack by scanning the rear face of the chip by laser pulses. The impact of the laser disrupts the functioning of the chip. It is the observation of the consequences of these disturbances, sometimes called faults, on the activity of the circuit, which allows the pirate to carry out his attack. To disrupt the operation of the chip, the hacker can also apply positive or negative potentials by means of a probe in contact with the rear face.
It is desirable to have electronic chips protected against this type of attack, known as fault injection attack, the known devices having various drawbacks and difficulties of implementation.
B15459 - 16-RO-0312
summary
Thus, one embodiment provides an electronic chip, comprising: a semiconductor substrate doped with a first type of conductivity; a buried layer doped with a second type of conductivity covering the substrate; a first doped box of the first type of conductivity covering the buried layer; separate circuits of the buried layer formed in and on the first box and / or in and on second boxes formed in the first box; and a polarization current detector of the buried layer.
According to one embodiment, a first wall of the second type of conductivity in contact with the buried layer surrounds the first box.
According to one embodiment, a second wall of the first type of conductivity in contact with the substrate surrounds the first wall.
According to one embodiment, between the buried layer and the second boxes, the first box has a thickness of between 2 and 3 μm.
According to one embodiment, the buried layer has a thickness of between 2 and 3 μm.
According to one embodiment, the detector is adapted to produce an alert signal when the bias current is, in absolute value, greater than a value between 2 and 50 pA.
One embodiment provides a method of protecting the above chip from attack, comprising: biasing the substrate and the first well to a reference potential; polarizing the buried layer so as to block the junction between the buried layer and the substrate and the junction between the buried layer and the first box; and producing an alert signal if the bias current of the buried layer is greater than a threshold, the alert signal triggering countermeasures to stop the attack.
B15459 - 16-RO-0312
Brief description of the drawings
These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures, among which:
Figures 1 and 2 are partial and schematic sectional views illustrating different types of circuit of an electronic chip;
FIG. 3A is a partial and schematic sectional view of an embodiment of an electronic chip protected against attacks;
Figure 3B is a schematic top view of the chip of Figure 3A; and FIG. 4 illustrates an embodiment of an attack detector.
detailed description
The same elements have been designated by the same references in the different figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed. In particular, details of analog or digital circuits and memory circuits are not shown.
In the description which follows, when reference is made to qualifiers of relative position, such as the terms above, below, upper, lower, etc., reference is made to the orientation of the element concerned in the views. in section concerned.
FIG. 1 is a sectional view illustrating an example of a circuit 10 of a first type, known as a double well (from the English double well), included in an electronic chip. Circuit 10 includes P channel MOS transistors TP and N channel MOS transistors TN. The TP transistors are formed in and on N-type doped boxes 12 located in the front face of a P-type substrate 14. The TN transistors are
B15459 - 16-RO-0312 formed in and on parts 16 of the substrate located between the boxes N 12. The boxes N 12 are provided with polarization contacts 18 on the front face. The contacts 18 are connected to an application node with a high VH potential. The parts 16 are provided with bias contacts 20 on the front face connected to a GND ground. The TP and TN transistors are connected, by conductors not shown, to form circuits supplied between high VH1 and low VL1 potentials. The supply potentials VH1 and VL1 can be respectively equal to the polarization potentials VH and GND. The TN, TP transistors and the bias contacts 18 and 20 are separated from each other by isolation trenches 22.
Figure 2 is a sectional view illustrating an example of a circuit 24 of a second type, called triple box (from the English triple well) included in an electronic chip. Circuit 24 incorporates elements of circuit 10 which will not be described again. In circuit 24, the wells N 12 are grouped together in a deep well 26 in which boxes P 16 are formed, and the polarization contacts 20 of the wells P 16 are connected to a node for applying a low potential VL which may be different from GND mass.
As indicated in the preamble, the circuits of a chip can contain confidential information coveted by a hacker. The hacker is likely to seek to obtain this information by a fault injection attack. For this, the hacker can first observe different circuits of the chip from the rear side by infrared camera, then select a circuit to attack.
The pirate can attack the circuit with a laser pulse 28. In the case of a double box type circuit as illustrated in FIG. 1, the pulse creates electro-hole pairs near the PN junction between a box N 12 and the substrate P 14. The electrons are separated by the electric field existing near the PN junction. The electrons go to the high potentials of the N 12 well and the
B15459 - 16-RO-0312 holes go towards the low potentials of a neighboring P 16 part. This results in a current IL which flows from the well N 12 towards the part P 16. The presence of electrons and holes, respectively in the well 12 and in the part 16, disturbs the operation of the transistors TN and TP. In the case of a triple box type circuit, the laser pulse creates a photocurrent IL1 from the well N 26 to the well P 16 and a photocurrent IL2 from the well N 2 6 to the substrate P 14, which disturbs the operation of the transistors.
The pirate can also attack the circuit by applying a potential, for example a positive potential of several tens of volts, by means of a not shown probe applied to the rear face. In the example of a triple box type circuit, the PN junction between the substrate P 14 and the box N 26 is directly polarized. A bipolar transistor consisting of a well P 16, of well N 26 and of substrate P 14 has its base-emitter junction polarized in direct and is therefore conducting. In this way, the pirate injects charges into the wells N 26 and P 16, which disturbs the operation of the TN and TP transistors.
We seek here to protect against such attacks circuits of the double box type or of the triple box type, these circuits can be digital circuits or analog circuits. It is also sought to protect other types of circuits, for example circuits comprising bipolar transistors and / or other types of semiconductor components and / or components such as capacitors or resistors. It is further sought to protect memory circuits, that is to say circuits comprising a set of memory points, for example an array of memory points.
FIGS. 3A and 3B illustrate an embodiment of a chip 30 protected against attacks by injection of faults. Figure 3A is a partial and schematic sectional view, and Figure 3B is a top view on a different scale.
B15459 - 16-RO-0312
By way of example, the chip 30 comprises a circuit 10 of the type of that of FIG. 1, a circuit 24 of the type of that of FIG. 2 and a memory circuit 32 (MEM) formed on the front face of a semiconductor wafer 33. The circuits 10, 24 and 32 illustrated in FIG. 3A are located in a protected area 34 (IC) visible in FIG. 3B where these circuits are not shown.
The chip 30 includes an N-type doped buried layer 36 located under a P-type doped layer 37. The circuits 10, 24 and 32 are formed in and on the layer 37. The P layer 37 is in contact with the buried layer 36 , on the other hand, the elements of circuits 10, 24 and 32 do not extend to the buried layer 36.
The periphery of the N-type buried layer 36 is in contact with an N-type doped wall 38 which extends, from the front face, into the part of the plate 33 located around the protected area 34. The layer 37, thus delimited by the buried layer 36 and by the wall 38, constitutes a box 37. As an example, the wall 38 completely surrounds the protected area 34. The wall 38 is surmounted by a contact 40 connected to a node 42 for applying a high potential for VDD polarization. The contact 40 is connected to a detector 44 (DET) of the bias current I of the buried layer 36, that is to say of the current absorbed by or buried by the buried layer 36. The detector can be located in protected area 34.
The part of the plate 33 located under the buried layer 36 corresponds to a P-type doped substrate 4 6. The substrate 4 6 is in contact with a P-type doped peripheral wall 48 which extends to the front face.
The wall P 48 is connected to ground GND by a contact 52 and the box P 37 is connected to ground GND by a contact 54.
By way of example, the wells N 12 and 26 of the circuits 10 and 24 can penetrate the well P 37 to a depth of less than 2 μm. The thickness of the box 37
B15459 - 16-RO-0312 between the lower level of the boxes N 12 and 26 and the upper level of the buried layer 36 can be between 2 and 3 μm. The buried layer 36 can have a thickness of between 2 and 3 μm.
In normal operation, that is to say in the absence of attack, the PN junctions between the buried layer 36 and the surrounding P-type doped regions 46 and 37 are reverse biased, and the bias current I of the buried layer 36 is negligible.
In the event of attack by a laser beam 28 from the rear face, a photogenerated current II flows from the buried layer 36 to the substrate P 46, and a photogenerated current 12 flows from the buried layer 36 to the box P 37. The bias current I of the buried layer 36, which comprises the two components II and 12, therefore increases due to the attack. When this current I becomes greater than a threshold, the detector emits an alert signal A. Following the generation of this alert signal, countermeasures are taken to stop the attack, for example by destroying the confidential data or by stopping the operation of the circuits.
Attacks are similarly detected and stopped by application of a positive or negative potential by a probe on the rear face of the chip. By way of example, the detected current threshold is in absolute value between 2 and 50 μ par, for example 10 μΑ.
According to an advantage, due to the presence of the buried layer N 36, it is possible to protect any type of circuit formed in the upper part of the box 37, and several circuits of different types can be protected simultaneously. In the example shown, a circuit of the double box type, a circuit of the triple box type and a memory circuit are protected. It is thus possible to simultaneously protect all the circuits of a chip.
According to another advantage, the box P 37, the wall N 38 and the wall P 48 occupy the front face around the protected area
B15459 - 16-RO-0312 a strip of small width, for example less than 4 μm. The surface of the chip dedicated to protection is limited to this band and to the surface of a single detector common to the circuits, while the protected zone 34 can be of surface greater than 1 mm 2. The area of the chip used to protect the circuits is therefore particularly limited.
According to another advantage, the detection sensitivity is particularly high. Indeed, due to the presence of the box P 37, the bias current generated by the attack is not mixed with the supply currents of the circuits or with the bias currents of the boxes included in the circuits.
According to another advantage, due to the presence of the buried N-type layer 36 sandwiched between regions P under all of the circuits of the protected area 34, the wells of the circuits are not visible by infrared imaging. This prevents the hacker from easily choosing the places to attack.
According to another advantage, the presence of the wall N 38 separated from the circuits surrounding the protected area 34 makes it possible to effectively protect the parts of the circuits situated on the periphery of the protected area.
FIG. 4 illustrates an example of a detector 44 adapted to detect a current entering or leaving the buried layer 36. The detector 44 is connected to the node for applying the potential λ / DD and to the contact 40 of the wall 38 connected to the buried layer 36. The PN junction between the substrate 46 connected to the contact 52 is represented by a diode 60 and by the diode 62 the PN junction between the box P 37 connected to the contact 54 and the buried layer 36.
The detector 44 includes a resistor 64 connecting the contact 40 to the node 42 for applying the potential λ / DD. Contact 40 is coupled by an inverter 66 to a first input of an OR gate 68. A comparator 70 is connected to the terminals of resistor 64, the positive input of comparator 70 being connected to contact 40 and the negative input being to the tension
B15459 - 16-RO-0312
VDD. The output of comparator 70 is connected to a second input of OR gate 68. The alert signal A corresponds to a high value of the output of OR gate 68.
In normal operation, the contact 40 is brought to the potential VDD through the resistor 64. No alert signal is emitted.
In the event of a laser attack causing the absorption by the buried layer of a current I, the potential of the contact 40 drops and the output of the inverter 66 goes to the high value, which causes the emission of the signal alert A. An attack is likewise detected by applying a high negative potential to the rear face.
In the event of an attack by application of a positive potential on the rear face, a current coming from the node 40 causes an increase in the potential of the contact 40, and this potential becomes greater than the potential VDD. When the potential of contact 40 exceeds a threshold value, the output of comparator 70 goes to the high value, which causes the emission of the alert signal A.
According to an advantage, the detector thus obtained contains a reduced number of components and is easy to implement. This detector occupies a limited area on the chip. In addition, this detector provides protection both against laser attacks and against attacks by application of a potential.
Particular embodiments have been described. Various variants and modifications will appear to those skilled in the art. In particular, although a resistor 64 has been described, in relation to FIG. 4, making it possible to apply the bias potential VDD to the contact 40, the resistor 64 can be replaced by a circuit for applying the potential VDD , this circuit supplying a current flowing towards the contact 40 when the potential of the contact 40 is lower than the potential VDD, and opposing a resistance to the passage of current from the contact 40 when the potential of the contact 40 is
B15459 - 16-RO-0312 greater than the potential λ / DD. The value of the current then corresponds to a detection threshold of the bias current.
In addition, although the walls 38 and 48 shown in Figure 3B completely surround the protected area 34, the walls of similar walls
In addition, the wall 38 connecting means and 48 can be replaced by partially surrounding the protected area can be replaced by any other electrically buried layer 36 at the detector 44.
In addition, the N and P conductivity types can be reversed by reversing the signs of the potentials.
B15459 - 16-RO-0312

权利要求:
Claims (4)
[1]
1. Electronic chip, comprising:
a semiconductor substrate (46) doped with a first type of conductivity;
a buried layer (36) doped with a second type of conductivity covering the substrate;
a first doped box (37) of the first type of conductivity covering the buried layer;
circuits (10, 24, 32) separate from the buried layer formed in and on the first box and / or in and on second boxes (12, 26, 16) formed in the first box; and a detector of the bias current (I) of the buried layer.
[2]
2. Chip according to claim 1, in which a first wall (38) of the second type of conductivity in contact with the buried layer (36) surrounds the first box (37).
[3]
3. A chip according to claim 2, in which a second wall (48) of the first type of conductivity in contact with the substrate (46) surrounds the first wall (38).
4. Chip according to one any of claims 1 to 3, in which, enter here buried layer and the second boxes (12, 26) , the first box (37) at a thickness understood between 2 and 3 pm. 5. Chip according to one any of claims 1 to 4, in which layer buried (36) at a thickness
between 2 and 3 pm.
6. Chip according to any one of claims 1 to 5, in which the detector (44) is adapted to produce an alert signal (A) when the bias current (I) is, in absolute value, greater than one value between 2 and 50 μΑ.
7. A method of protecting a chip according to any one of claims 1 to 6 against an attack, comprising:
B15459 - 16-RO-0312 polarize the substrate (46) and the first well (37) at a reference potential (GND);
polarizing the buried layer (36) so as to block the junction between the buried layer and the substrate and the
[4]
5 junction between the buried layer and the first box; and producing an alert signal (A) if the bias current (I) of the buried layer is greater than a threshold, the alert signal triggering countermeasures to stop the attack.
B15459
1/3
B15459
2/3) GND

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法律状态:
2017-08-21| PLFP| Fee payment|Year of fee payment: 2 |

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2018-04-06| PLSC| Search report ready|Effective date: 20180406 |

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2018-08-22| PLFP| Fee payment|Year of fee payment: 3 |

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2020-10-16| ST| Notification of lapse|Effective date: 20200906 |

优先权:

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申请号 | 申请日 | 专利标题

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FR1659451|2016-09-30|

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FR1659451A|FR3057087B1|2016-09-30|2016-09-30|PROTECTED ELECTRONIC CHIP|FR1659451A| FR3057087B1|2016-09-30|2016-09-30|PROTECTED ELECTRONIC CHIP|

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EP17156779.5A| EP3301605B1|2016-09-30|2017-02-17|Protected electronic chip|

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US15/444,644| US10141396B2|2016-09-30|2017-02-28|Protected electronic chip|

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CN201710179661.9A| CN107887337B|2016-09-30|2017-03-23|Protected electronic chip|

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CN201720293585.XU| CN206685382U|2016-09-30|2017-03-23|Electronic chip|

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US16/161,785| US10388724B2|2016-09-30|2018-10-16|Protected electronic chip|